Basic Block of Pipelined ADC Design Requirements
نویسندگان
چکیده
The paper describes design requirements of a basic stage (called MDAC Multiplying Digital-toAnalog Converter) of a pipelined ADC. There exist error sources such as finite DC gain of opamp, capacitor mismatch, thermal noise, etc., arising when the switched capacitor (SC) technique and CMOS technology are used. These non-idealities are explained and their influences on overall parameters of a pipelined ADC are studied. The pipelined ADC including non-idealities was modeled in MATLAB Simulink simulation environment.
منابع مشابه
Low Power SC Pipelined ADC Using Op-Amp Sharing Approach
The paper describes a case study of new 12-bit low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioural modelling regarding low power consumption. It is reached by Op-Amp sharing technique utilisation. The basic block topology design is outlined too. The cancellation techniques for avoiding of capacitor mismatch, clock feed...
متن کاملNew Switched-Capacitor Pipelined ADC
The paper deals with a new 12-bit low power switched-capacitor (SC) ADC for portable applications, such PDA, notebook etc. The paper describes design of ADC and its behavioural modelling regarding low power consumption. The Op-Amp sharing technique and capacitor scaling approach are utilized to obtain it. The basic block topology design is outlined too. The cancellation techniques to avoid the ...
متن کاملComparative Analysis of Two Op-Amp Topologies for a 40MS/s 8-bit Pipelined ADC in 0.18μm CMOS Technology
The performances of two full differential operational amplifiers (Op-Amps) telescopic and foldedcascode are evaluated to satisfy the stringent requirements on the amplifier to be used in a Multiplying Digitalto-Analog Converter (MDAC) stage of a pipelined ADC (Analog-to-Digital Converter). The paper shows the solutions found to reach high gain, wide bandwidth and short settling time without deg...
متن کاملA Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture
This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained resu...
متن کاملDesign and Implementation of Low Power 12-Bit 100-MS/s Pipelined ADC Using Open-Loop Residue Amplification
In this paper a high speed, low power 12-bit, analog-to-digital converter in CMOS 0.13 micron technology that makes it suitable for UWB is designed and implemented. For designing the particular ADC a bottom up hierarchical method is adopted. First according to the specification, the design of aspect ratio of the transistors used in our design is done. There were many challenges throughout the d...
متن کامل